----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:59:25 11/09/2010 
-- Design Name: 
-- Module Name:    counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use WORK.CONSTANTS.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IJTAG_counter is
    Port ( seed : in  STD_LOGIC_VECTOR(DATA_SIZE_IJTAG-1 downto 0);
           update : in  STD_LOGIC;
			  reset : in STD_LOGIC;
           count : out  STD_LOGIC_VECTOR(DATA_SIZE_IJTAG-1 downto 0);
           clk : in  STD_LOGIC);
end IJTAG_counter;

architecture Behavioral of IJTAG_counter is



begin
P_counter : process(clk, reset, seed, update)

	
	variable temp_int : integer range 0 to 7 := 0;

	-- purpose : Implements an incrementing modulo 8 counter working in the clock's falling edge
	-- type    : Behavioral 
	begin
		if reset = '1' then
			temp_int	:= 0;
		elsif clk'event and clk = '0' then
			if update='1' then
				temp_int	:= conv_integer(unsigned(seed));
			else
				if (temp_int < 7) then 
				temp_int	:= temp_int + 1;
				else 
				temp_int := 0;
				end if;			
			end if;
		end if;
		count	<= conv_std_logic_vector(temp_int, DATA_SIZE_IJTAG); -- convert int to std_logic	
	end process;
	
end Behavioral;

